1. Field of the Invention
The present invention relates to a method for fabricating a superlattice semiconductor structure using chemical vapor deposition. More particularly, the present invention relates to a method for fabricating a superlattice semiconductor structure capable of improving interfacial properties of a superlattice and attaining uniformity within and among substrates.
2. Description of the Related Art
With the recent drastic development in Light Emitting Diode (LED) or optoelectronic device using compound semiconductor such as AlGaInP, there is a rising demand for a superlattice semiconductor structure. For example, in fabricating group III-V semiconductor device, a buffer layer of the superlattice semiconductor structure can be formed between a substrate and a group III-V semiconductor layer, to solve problems caused by differences in lattice constant and thermal expansion coefficient between substrate material and group III-V compound semiconductor material. The superlattice semiconductor structure reportedly has advantages of inhibiting crystalline defects such as dislocation and improving electrical conductivity. Also, electron overflow can be prevented by forming an active layer of LED as a superlattice multiple quantum well structure. In addition, the superlattice semiconductor structure is greatly utilized in photonic crystal field. U.S. Pat. No. 6,706,585 discloses a method for fabricating layered superlattice materials via chemical vapor deposition. FIG. 1 is a schematic view of a compound semiconductor device with a general superlattice structure. Epitaxial layers 13, 14 of different compositions are stacked alternately and repeatedly on a substrate to form the superlattice structure. For example, the superlattice structure can be fabricated by stacking GaAs layer 13 and AlAs layer 14 alternately on the sapphire substrate 11.
However, to form the superlattice semiconductor structure requires regular and repeated growth of an ultrathin layer, which however renders it difficult to obtain uniformity and reproducibility of the superlattice structure in large-sized batch-type equipment. Further, interfacial properties of the superlattice structure are an influencing factor for properties of a total superlattice structure. But problems arising from fabrication process or fabrication equipment easily deteriorate interfacial properties of the superlattice structure.
FIG. 2 is a timing diagram for explaining a conventional method for fabricating a superlattice semiconductor structure. FIG. 3 is a schematic flow diagram of a metal-organic chemical vapor deposition (MOCVD) apparatus applied to a conventional fabrication method of FIG. 2. Conventionally, for example, to form the superlattice semiconductor structure of FIG. 1, an MOCVD process is utilized to supply different source gases alternately and repeatedly to a process chamber. Source gases are introduced into the reaction chamber to form and deposit the semiconductor layers.
Referring to the timing diagram of FIG. 2, “ON” indicates that corresponding source gas is being supplied to the process chamber (chamber mounted with a substrate), while “OFF” indicates that corresponding source gas is not being supplied to the chamber (supply stopped). A first source gas, for example, may be source gas for forming GaAs layer 13 (e.g. trimetil galum (TMG)), while a second source gas may be source gas for forming AlAs layer 14 (e.g. trimetil aluminium (TMA)) (refer to FIG. 1). As shown in FIG. 2, the first source gas (TMG) is supplied to the process chamber to form GaAs layer 13 on the substrate mounted within the process chamber. Thereafter, supply of the first source gas is halted, and the second source gas is supplied to the process chamber to form AlAs layer 14 on the GaAs layer 13. The superlattice semiconductor structure can be attained by repeating such one cycle process, as shown in FIG. 1.
Referring to a flow diagram of FIG. 3, a first source gas is continuously supplied by s first source gas supplier 41 through a gas controller 43 and then flows to a switching valve 49. At the same time, a second source gas is continuously supplied by a second source gas supplier 42 through a gas controller 44 and then flows to a switching valve 46. Each of the switching valves 49, 46 performs on/off operation. In the case of ‘on’ operation, corresponding source gas is supplied to a process chamber 70, whereas in the case of ‘off’ operation, corresponding source gas is exhausted into a vent. Each of the switching valves 49, 48 performs on/off operation alternately and thus only one of the first and second source gases is supplied through a nozzle 20 to a substrate 11 mounted on a susceptor or a susceptor 30. The susceptor 30 continues to be rotated during the process in order to revolve a plurality of substrates.
That is, as shown in FIGS. 2 and 3, while the first switching valve 49 is ON, the second switching valve 46 is OFF. Thus, only the first source gas (e.g. TMG) is supplied through a source gas introduction line 48 to the process chamber 70, while the second source gas (e.g. TMA) is exhausted into the vent 46a. 
On the contrary, while the first switching valve 49 is OFF, the second switching valve 46 is ON. Consequently, only the second source gas is supplied to the process chamber 70, while the first source gas is exhausted into the vent 46a. 
During supply of the first or second source gas, a third source gas (e.g, AsH3, source gas of As) may be supplied through the source gas introduction line 47 and the nozzle 20 to the process chamber 70. Residual gas after reaction in the chamber 70 is exhausted outside through an exhaustion line 61. Repetition of such operation allows fabrication of the superlattice semiconductor structures 13, 14 as shown in FIG. 1.
However, according the aforesaid method for fabricating the superlattice semiconductor structure, the switching valve is selectively switched, causing half of source gas to be exhausted into the vents 49a, 46a and thus unnecessarily increasing purchase price of source gas. Further, the switching valves are placed at a considerable distance from the process chamber so that it takes great time for a desired semiconductor layer to grow after switching of source gas. In addition, it takes substantial time before source gas is evenly spread to ensure uniform growth of the semiconductor layer in a batch-type process chamber. Such time requirement deteriorates interfacial properties of the superlattice, impairs uniformity within and among the substrates and leads to low reproducibility. Also, the aforesaid time requirement and difficult control of on/off operation prolongs process time and complicates process.